The present application relates to semiconductor fins for FinFET devices, and particularly to semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same.
FinFET devices are widely used in the semiconductor industry. However, there may be difficulties associated with the manufacture of the semiconductor fins for the FinFET devices.
For instance, high atomic percentage germanium (Ge) channels are currently being proposed as channel materials for future nodes. However, with conventional methods, it is almost impossible to form stable high atomic % germanium films without significant physical/damage occurring to these high atomic % germanium films caused by wet etching processes and/or dry etching processes (e.g., RIE) when taking these films downstream.
In addition, another difficulty with manufacturing semiconductor fins for FinFET devices is that a tight fin pitch may be needed for continued scaling of FinFET to 7 nm nodes and beyond. However, 7 nm nodes calls for 28 nm fin pitch which is well beyond conventional lithography patterning and even conventional sidewall transfer image (SIT) techniques. Currently, double SIT (SIT2) is being used in an attempt to form semiconductor fins with a tight pitch for a 7 nm node. SIT2 basically repeats the conventional SIT process. However, since conventional SIT2 processes form mandrels on different levels of a wafer from one another there may be certain drawbacks associated with these conventional processes. For instance, one the drawbacks to using conventional SIT2 processes is that it increases manufacturing costs. In addition, another drawback to conventional SIT2 processes is the difficulty in cutting (removing) the unwanted semiconductor fins after SIT2 due to the tight fin pitch (semiconductor fins are closely spaced and therefore it is difficult to completely cut the unwanted fin without compromising the adjacent device semiconductor fins).